A microprocessor that is capable of issuing and executing machine instructions out of order will in general permit loads to be executed ahead of stores. This feature permits a large performance advantage provided that the load address and the store address do not both have the same physical address. In typical programs, the frequency that a load proceeds ahead of the store and that their physical address matches is low. However, since the discovery of this store violation condition is typically late in the instruction execution pipeline, the recovery penalty can be quite severe. For example, the recovery process typically involves invalidating the load instruction that caused the violation and all newer instructions in program order beyond the load instruction, and second reissuing the load instruction. Conventional mechanisms for managing store-compare hazards generally do not manage these hazards very effectively.